In Direct Sequence Spread Spectrum of a Code Division Multiple Access (CDMA) system, a high rate spread spectrum sequence with pseudo-random noise properties is usually adopted to spread the frequency of the lower rate base band signal, thereby obtaining a channel spread spectrum gain to improve the transmission quality of signals. In a receiver, the same spread spectrum sequence is used to perform opposite processing on the received signal, i.e. despreading processing, to restore the original data information. An important factor here is the synchronization between the transmitter and receiver. In general, a pre-defined sequence usually called SC (i.e. synchronization code) is inserted in each sub-frame for frame synchronization, and also a pre-defined known sequence (training sequence) is inserted in each time slot for time slot synchronization in the DS-CDMA (Direct Spread-Code Divided Multiple Access) system, the receiving terminal can achieve the signal synchronization between the transmitter and received just through performing matched filtering (correlation) on the pre-defined known sequence.
A conventional system of CDMA receiver is, in general, designed to realize the synchronization by using the matched filter containing a large amount of electronic components, wherein the matched filter occupies a larger area and the implementation thereof is more expensive. Especially, a CDMA receiver uses a matched filter to match a code sequence to detect the correlation peak. A matched filter comprises, in general, a delay register, a multiplier and an adder. Since the matched filter needs to contain a large amount of electronic components, the design of system is expensive and the system occupied a larger area.
Now referring to FIG. 1, this figure shows the function of the matched filter accomplished in a CDMA receiver. When a receiver receives an input signal, the matched filter is tuned to match a code sequence. In systems using Quadrature-Phase-Shift-Keying (QPSK) modulation, such as the TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) systems, the code sequence is inserted in the signals (i.e. digital sample) received by the receiver. The object of providing a code sequence is to enhance the operation of communication systems. Particularly, in CDMA wireless communication systems, the spread spectrum technology is very suitable to provide stable data transmission in a wireless environment with severe interference.
On the other hand, in CDMA systems, multiple users share communication channels on the same spectrum and in the same time. In order to discriminate one transmission from another, every UE (User Equipment) has a unique synchronization code sequence. The synchronization sequence usually has a good auto-correlation performance, so it helps UE to identify the synchronization code rapidly and accurately without any prior knowledge about timing reference and also helps base station to discriminate different code used by different UE. In implementation, a matched filter is usually used for synchronization and discrimination of different UE in DS-CDMA system. Just as shown in FIG. 1, a matched filter 1 comprises a matched filter unit 2 and a detection unit 3, wherein the matched filter unit 2 is used to perform matched filtering on the code sequence in an input data stream, the detection unit 3 is used to detect the matched filter output from the matched filter unit 2, wherein a higher output value of the matched filter unit 2 indicates a more tuned match with the expected code sequence. This process is also called correlation process. Hence a high output value represents a good correlation of input with the code sequence of interest. What is more, in flat-fading channel, the peak output value within a sub-frame/time slot can be used as the channel estimation value for this sub-frame/time slot.
Referring to FIG. 2, this figure shows a schematic diagram illustrating a Finite Impulse Response (FIR) filter for implementing matched filters in prior art. Just as shown in FIG. 2, to match a code sequence with length L, L delay registers, L multiplier and L adders are needed. That is to say, in the prior art, more hardware components are needed to realize the matched filter. And it is commonly known that the hardware implementation of a multiplier is more complex.
In view of the above reasons, it's needed to provide a new hardware implementation of matched filters to realize the desired function of matched filter by using less electronic components and relatively more simple hardware structure.